The fabrication of various solid state devices requires the use of planar substrates, or semiconductor wafers, on which integrated circuits are fabricated. The final number, or yield, of functional integrated circuits on a wafer at the end of the IC fabrication process is of utmost importance to semiconductor manufacturers, and increasing the yield of circuits on the wafer is the main goal of semiconductor fabrication. After packaging, the circuits on the wafers are tested, wherein non-functional dies are marked using an inking process and the functional dies on the wafer are separated and sold. IC fabricators increase the yield of dies on a wafer by exploiting economies of scale. Over 1000 dies may be formed on a single wafer which measures from six to twelve inches in diameter.
Various processing steps are used to fabricate integrated circuits on a semiconductor wafer. These steps include deposition of a conducting layer on the silicon wafer substrate; formation of a photoresist or other mask such as titanium oxide or silicon oxide, in the form of the desired metal interconnection pattern, using standard lithographic or photolithographic techniques; subjecting the wafer substrate to a dry etching process to remove the conducting layer from the areas not covered by the mask, thereby etching the conducting layer in the form of the masked pattern on the substrate; removing or stripping the mask layer from the substrate typically using reactive plasma and chlorine gas, thereby exposing the top surface of the conductive interconnect layer; and cooling and drying the wafer substrate by applying water and nitrogen gas to the wafer substrate.
The numerous processing steps outlined above are used to cumulatively apply multiple electrically conductive and insulative layers on the wafer and pattern the layers to form the circuits. The final yield of functional circuits on the wafer depends on proper application of each layer during the process steps. Proper application of those layers depends, in turn, on coating the material in a uniform spread over the surface of the wafer in an economical and efficient manner.
As integrated circuits decrease in size, delays associated with the wiring in the circuits have become increasingly important. To reduce such delays, it is necessary to reduce the resistance of the wires and/or the capacitance per unit length across the inter-metal dielectrics. Wire widths in integrated circuits have, however, continued to shrink such that the electrical conductivity of the wiring material itself has become increasingly more important. Therefore, aluminum is increasingly being replaced by copper.
Similarly, silicon dioxide, which has traditionally been the inter-metal dielectric (IMD) of choice in the semiconductor industry, is being increasingly replaced by dielectric materials having a lower dielectric constant. An example of a dielectric material with low dielectric constant in widespread usage is fluorinated silicon glass (FSG), which typically has a dielectric constant of below 3.9.
Integrated circuits having both copper wiring and FSG as the IMD layer are in widespread use. One of the problems associated with the use of copper in copper interconnect is the tendency of copper to diffuse quickly and serve as a source of recombination centers in silicon. Several materials are known to retard diffusion of copper at room temperature. However, these materials cannot be relied upon to serve as a barrier against copper diffusion when conventional multi-layering is used due to the difficulty of using the materials to cover the edges of the wiring.
The wiring coverage problem has been solved using damascene wiring techniques. In a damascene wiring structure, rather than being covered by a supporting medium, a layer is inlaid within the medium. Therefore, instead of depositing an IMD layer and then fabricating the wiring structure on top of the IMD layer, a trench is first formed in the IMD layer after which the trench is filled with copper to form the copper wiring. The walls of the trench are lined with a barrier layer prior to deposition of the copper in the trench.
Referring to FIG. 1, a conventional damascene structure 10 includes a substrate 12 on which is typically provided a metal line 20. An FSG layer 14 is deposited as an intermetal dielectric (IMD) layer on the substrate 12 and metal line 20. A via opening 16 is etched through the FSG layer 14 to expose the surface of the metal line 20. A barrier layer 18 is deposited on the sidewalls and bottom of the via opening 16, after which a copper inlay 22 is deposited in the via opening 16, on the barrier layer 18 to form the copper wiring. The copper-filling step is carried out typically by over-filling the via opening 16 using electrochemical plating techniques, followed by removal of the copper overburden using chemical mechanical polishing (CMP).
The FSG layer 14 is formed on the substrate 12, typically, by reacting SiF4/SiH4 gas with oxidizer to form fluorinated silicate glass (F—SiO) in a chemical vapor deposition (CVD) chamber. Simultaneously, RF power is applied to the reactant gases to form a plasma in the chamber. After the main deposition step, ionized gases which contain various free radicals such as SiF3*, SiF2*, SiF*, Si*, H*, O* and F*, as well as unreacted SiF4, all possibly remain in the chamber. These could have a tendency that contains Fluorine reactive gases and/or radical to chemically attack and/or to form the defects on the deposited FSG layer as well as subsequent processes, ex., forming the metal structures in devices being fabricated on the wafer, resulting in the instabilities in the devices.
Furthermore, during etching of the via opening 16 in the FSG layer 14, as well as during the post-filling CMP process, the FSG layer 14 is frequently exposed. Fluoride ions come from incomplete reaction and/or residual of F-containing gases during processing are loosely bound in the FSG layer 14. Consequently, highly-reactive fluorine radicals are released from the FSG layer 14. The fluorine radicals tend to react with the surface and sidewalls of the FSG layer 14, as well as with the copper inlay 22 (in the case of a CMP process) and moisture, resulting in outgassing, formation of defect structures in the FSG layer 14 and corrosion of the copper inlay 22.
Accordingly, an in-situ method is needed for eliminating the presence of fluorine and fluorine-containing radicals from a process chamber and an FSG layer after formation of the FSG layer on a substrate. Furthermore, an ex-situ method is needed for eliminating fluorine ions from an FSG layer after an etching process or a CMP process.
Accordingly, an object of the present invention is to provide a method for enhancing the stability of an FSG layer or film.
Another object of the present invention is to provide a method for preventing or reducing the incidence of radical-induced defects caused by damage to an FSG layer.
Still another object of the present invention is to provide an in-situ method for enhancing FSG film stability after formation of an FSG layer.
Yet another object of the present invention is to provide an ex-situ method for enhancing FSG film stability after an etching process or CMP process.
A still further object of the present invention is to provide a method for enhancing FSG layer stability, which method includes subjecting an FSG layer to PH3 after formation of the FSG layer or after an etching or CMP process.